1. Field of the Invention
Embodiments of the invention generally relate to electronic design automation and, more specifically, to a method and apparatus for event-based simulation of a digital design having a power shut-off feature.
2. Description of the Related Art
In electronic design automation (EDA), functional verification is the task of verifying that a logic design conforms to its specification before the logic design is manufactured as integrated circuits (ICs). Functional verification can be performed using an event driven digital logic simulation system. Digital logic simulation systems simulate the functional behavior of a digital design and verify its correctness. Traditional logic simulation systems work under the assumption that the digital design is always powered-on. However, with semiconductor manufacturing feature size getting ever smaller and with ICs getting ever more complex, power consumption becomes a significant obstacle in digital design.
Power shut off (PSO) has emerged as a leading design technique to reduce power consumption in complex digital ICs. In PSO, a portion of a digital design is powered-down when unused, while another portion continues to operate, in order to conserve power. PSO poses significant challenges to the digital design verification process. Since traditional logic simulation systems assume an always powered-on state, such systems cannot adequately be used to functionally verify digital designs that employ PSO techniques.
Accordingly, there exists a need in the art for a logic verification system that can simulate digital designs employing PSO features.